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CY7C1212H
1-Mbit (64K x 18) Pipelined Sync SRAM
Features
* Registered inputs and outputs for pipelined operation * 64K x 18 common I/O architecture * 3.3V core power supply (VDD) * 2.5V/3.3V I/O power supply (VDDQ) * Fast clock-to-output times -- 3.5 ns (for 166-MHz device) * Provide high-performance 3-1-1-1 access rate * User-selectable burst counter supporting Intel(R) Pentium(R) interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed write * Asynchronous output enable * Available in JEDEC-standard lead-free 100-Pin TQFP package * "ZZ" Sleep Mode Option
Functional Description[1]
The CY7C1212H SRAM integrates 64K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written. The CY7C1212H operates from a +3.3V core power supply while all outputs may operate either with a +2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
Logic Block Diagram
A0, A1, A
MODE
ADDRESS REGISTER
2
A[1:0]
ADV CLK
BURST Q1 COUNTER AND CLR LOGIC Q0
ADSC
ADSP DQB,DQPB WRITE REGISTER DQB,DQPB WRITE DRIVER MEMORY ARRAY BWA BWE GW CE1 CE2 CE3 OE ENABLE REGISTER DQA,DQPA WRITE REGISTER DQA,DQPA WRITE DRIVER SENSE AMPS
BWB
OUTPUT REGISTERS
OUTPUT BUFFERS
E
DQs DQPA DQPB
PIPELINED ENABLE
INPUT REGISTERS
Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05668 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised July 6, 2006
CY7C1212H
Selection Guide
166 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 3.5 240 40 133 MHz 4.0 225 40 Unit ns mA mA
Pin Configuration 100-Pin TQFP
Top View
NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC
BYTE B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
CY7C1212H
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC
BYTE A
Document #: 38-05668 Rev. *B
MODE A A A A A1 A0 NC/72M NC/36M VSS VDD NC/18M NC/9M A A A A A NC/2M NC/4M
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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CY7C1212H
Pin Definitions
Name A0, A1, A I/O InputSynchronous InputSynchronous InputSynchronous InputSynchronous InputClock InputSynchronous InputSynchronous InputSynchronous Description Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0 feed the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global Write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a Byte Write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Not connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded.
BWA,BWB GW BWE CLK CE1
CE2
CE3
OE
InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected state. InputSynchronous InputSynchronous Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ADV ADSP
ADSC
InputSynchronous
ZZ
InputZZ "Sleep" Input, active HIGH. This input, when HIGH places the device in a non-time-critical Asynchronous "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by "A" during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a tri-state condition. Ground for the device. Power supply for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode pin has an internal pull-up. No Connects. Not internally connected to the die. 2M, 4M, 9M,18M, 72M, 144M, 288M, 576M and 1G are address expansion pins and are not internally connected to the die.
DQs DQPA, DQPB VDD VSS VDDQ MODE
Power Supply Power supply inputs to the core of the device. Ground I/O Power Supply InputStatic
NC
Document #: 38-05668 Rev. *B
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CY7C1212H
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1212H supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486TM processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All Writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the address register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tCO if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BW[A:B]) and ADV inputs are ignored during this first cycle. ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQ inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the Write operation is controlled by BWE and BW[A:B] signals. The CY7C1212H provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW[A:B]) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1212H is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BW[A:B]) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to DQs is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1212H is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1212H provides a two-bit wraparound counter, fed by A1, A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Document #: 38-05668 Rev. *B
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CY7C1212H
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00
Linear Burst Address Table (MODE = GND)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ Active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 40 2tCYC Unit mA ns ns ns ns
Truth Table[2, 3, 4, 5, 6, 7]
Next Cycle Unselected Unselected Unselected Unselected Unselected Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read Begin Write Add. Used None None None None None External External Next Next Next Next Current Current Current Current Current CE1 H L L L L L L X X H H X X H H X CE2 X X L X L H H X X X X X X X X X CE3 X H X H X L L X X X X X X X X X ZZ L L L L L L L L L L L L L L L L ADSP X L L H H L H H H X X H H X X H ADSC L X X L L X L H H H H H H H H H ADV X X X X X X X L L L L H H H H H OE X X X X X X X H L H L H L H L X DQ Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State DQ Tri-State DQ Tri-State DQ Tri-State DQ Tri-State Write X X X X X X Read Read Read Read Read Read Read Read Read Write
Notes: 2. X = "Don't Care." H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write Enable signals (BWA,BWB) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA,BWB), BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. CE1, CE2, and CE3 are available only in the TQFP package. 6. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:B]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the Write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05668 Rev. *B
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CY7C1212H
Truth Table[2, 3, 4, 5, 6, 7] (continued)
Next Cycle Begin Write Begin Write Continue Write Continue Write Suspend Write Suspend Write ZZ "Sleep" Add. Used Current External Next Next Current Current None CE1 H L X H X H X CE2 X H X X X X X CE3 X L X X X X X ZZ L L L L L L H ADSP X H H X H X X ADSC H H H H H H X ADV H X H H H H X OE X X X X X X X DQ Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State Write Write Write Write Write Write Write X
Truth Table for Read/Write[2, 3]
Function Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write All Bytes Write All Bytes GW H H H H H L BWE H L L L L X BWB X H H L L X BWA X H L H L X
Document #: 38-05668 Rev. *B
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CY7C1212H
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied............................................ -55C to + 125C Supply Voltage on VDD Relative to GND....... -0.5V to + 4.6V Supply Voltage on VDDQ Relative to GND ..... -0.5V to + VDD DC Voltage Applied to Outputs in Tri-State........................................... -0.5V to VDDQ + 0.5V Range Commercial Industrial DC Input Voltage ................................... -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA
Operating Range
Ambient Temperature 0C to +70C -40C to +85C VDD VDDQ 3.3V 2.5V -5% to -5%/+10% VDD
Electrical Characteristics Over the Operating Range[8, 9]
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[8] Input LOW Voltage[8] Input Leakage Current except ZZ and MODE for 3.3V I/O for 2.5V I/O for 3.3V I/O, IOH = -4.0 mA for 2.5V I/O, IOH = -1.0 mA for 3.3V I/O, IOL = 8.0 mA for 2.5V I/O, IOL = 1.0 mA for 3.3V I/O for 2.5V I/O for 3.3V I/O for 2.5V I/O GND VI VDDQ 2.0 1.7 -0.3 -0.3 -5 -30 5 -5 30 -5 5 240 225 100 90 40 mA 6-ns cycle,166 MHz 7.5-ns cycle,133 MHz 6-ns cycle,166 MHz 7.5-ns cycle,133 MHz Test Conditions Min. 3.135 3.135 2.375 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max. 3.6 VDD 2.625 Unit V V V V V V V V V V V A A A A A A mA mA mA
Input Current of MODE Input = VSS Input = VDD Input Current of ZZ IOZ IDD ISB1 Input = VSS Input = VDD Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply Current Automatic CS Power-down Current--TTL Inputs VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC VDD = Max, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC
ISB2
Automatic CS VDD = Max, Device Deselected, All speeds Power-down VIN 0.3V or VIN > VDDQ - 0.3V, Current--CMOS Inputs f = 0 Automatic CS VDD = Max, Device Deselected, or 6-ns cycle,166 MHz Power-down VIN 0.3V or VIN > VDDQ - 0.3V 7.5-ns cycle,133 MHz Current--CMOS Inputs f = fMAX = 1/tCYC Automatic CS Power-down Current--TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL, f = 0 All speeds
ISB3
85 75 45
mA mA mA
ISB4
Notes: 8. Overshoot: VIH(AC) < VDD+1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 9. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05668 Rev. *B
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CY7C1212H
Capacitance[10]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V. VDDQ = 2.5V 100 TQFP Max. 5 5 5 Unit pF pF pF
Thermal Resistance[10]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 100 TQFP Package 30.32 6.85 Unit C/W C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 5 pF INCLUDING JIG AND SCOPE R = 351 R = 317 VDDQ 10% GND 1 ns ALL INPUT PULSES 90% 90% 10% 1 ns
VT = 1.5V (a)
(b)
R = 1667 VDDQ 10%
(c)
2.5V I/O Test Load
OUTPUT Z0 = 50 2.5V OUTPUT RL = 50 5 pF VT = 1.25V INCLUDING JIG AND SCOPE
ALL INPUT PULSES 90% 90% 10% 1 ns
GND R =1538 1 ns
(a)
(b)
(c)
Note: 10. Tested initially and after any design or process change that may affect these parameters.
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CY7C1212H
Switching Characteristics Over the Operating Range[11, 12]
166 MHz Parameter tPOWER Clock tCYC tCH tCL tCO tDOH tCLZ tCHZ tOEV tOELZ tOEHZ tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tADVH tWEH tDH tCEH Address Hold after CLK Rise ADSP, ADSC Hold after CLK Rise ADV Hold after CLK Rise GW, BWE, BW[A:B] Hold after CLK Rise Data Input Hold after CLK Rise Chip Enable Hold after CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW Data Output Valid after CLK Rise Data Output Hold after CLK Rise Clock to Low-Z
[14, 15, 16]
133 MHz Min. 1 7.5 3.0 3.0 Max. Unit ms ns ns ns 4.0 1.5 0 ns ns ns 4.0 4.5 0 4.0 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns ns ns ns ns
Description VDD(Typical) to the First Access
[13]
Min. 1 6.0 2.5 2.5
Max.
Output Times 3.5 1.5 0 3.5 3.5 0 3.5 1.5 1.5 1.5 1.5 1.5 1.5
Clock to High-Z[14, 15, 16] OE LOW to Output Valid OE LOW to Output OE HIGH to Output Low-Z[14, 15, 16] High-Z[14, 15, 16]
Set-up Times Address Set-up before CLK Rise ADSC, ADSP Set-up before CLK Rise ADV Set-up before CLK Rise GW, BWE, BW[A:B] Set-up before CLK Rise Data Input Set-up before CLK Rise Chip Enable Set-Up before CLK Rise
Notes: 11. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 12. Test conditions shown in (a) of AC Test Loads unless otherwise tested. 13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation can be initiated. 14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 16. This parameter is sampled and not 100% tested.
Document #: 38-05668 Rev. *B
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CY7C1212H
Switching Waveforms
Read Cycle Timing[17]
t CYC
CLK
t CH t ADS t ADH
t CL
ADSP
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
tWES tWEH
A2
A3 Burst continued with new base address
GW, BWE, BW[A:B]
tCES tCEH
Deselect cycle
CE
tADVS tADVH
ADV ADV suspends burst.
tOEV t OEHZ t CLZ t OELZ tCO tDOH t CHZ
OE
Data Out (Q)
High-Z
Q(A1)
t CO
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Single READ DON'T CARE UNDEFINED
BURST READ
Burst wraps around to its initial state
Note: 17. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
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CY7C1212H
Switching Waveforms (continued)
Write Cycle Timing[17, 18]
t CYC
CLK tCH tADS ADSP ADSC extends burst tADS tADH tADH tCL
tADS ADSC tAS A1 tAH
tADH
ADDRESS
A2 Byte write signals are ignored for first cycle when ADSP initiates burst
A3
tWES tWEH
BWE, BW[A :D] tWES tWEH GW tCES CE t t ADVS ADVH ADV ADV suspends burst tCEH
OE tDS tDH
Data In (D)
High-Z
t OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE
DON'T CARE
UNDEFINED
Note: 18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.
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CY7C1212H
Switching Waveforms (continued)
Read/Write Cycle Timing[17, 19, 20]
tCYC
CLK
tCH tADS tADH tCL
ADSP
ADSC
tAS tAH
ADDRESS BWE, BW[A:B]
A1
A2
A3 tWES tWEH
A4
A5
A6
tCES
tCEH
CE
ADV
OE
tCO tDS tDH tOELZ High-Z tCLZ tOEHZ Q(A2) Single WRITE D(A3) D(A5) D(A6)
Data In (D)
Data Out (Q)
High-Z
Q(A1) Back-to-Back READs
Q(A4)
Q(A4+1) BURST READ
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
DON'T CARE
UNDEFINED
Notes: 19. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed. 20. GW is HIGH.
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CY7C1212H
Switching Waveforms (continued)
ZZ Mode Timing[21, 22]
CLK
t ZZ t ZZREC
ZZ
t
ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05668 Rev. *B
Page 13 of 15
CY7C1212H
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 100 133 Ordering Code CY7C1212H-100AXC CY7C1212H-100AXI CY7C1212H-133AXC CY7C1212H-133AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Package Diagram Package Type Operating Range Commercial Industrial Commercial Industrial
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Package Diagrams
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.000.20 14.000.10
100 1 81 80
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0 MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0-7
R 0.08 MIN. 0.20 MAX.
0.600.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050-*B
A
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05668 Rev. *B
0.10
R 0.08 MIN. 0.20 MAX.
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1212H
Document History Page
Document Title: CY7C1212H 1-Mbit (64K x 18) Pipelined Sync SRAM Document Number: 38-05668 REV. ** *A ECN NO. 343896 430677 Issue Date See ECN See ECN Orig. of Change PCI NXR New Data Sheet Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Added 2.5VI/O option Changed Three-State to Tri-State Included Maximum Ratings for VDDQ relative to GND Modified "Input Load" to "Input Leakage Current except ZZ and MODE" in the Electrical Characteristics Table Modified test condition from VIH < VDD to VIH < VDD Replaced Package Name column with Package Diagram in the Ordering Information table Converted from Preliminary to Final. Updated the Ordering Information table. Description of Change
*B
482139
See ECN
VKN
Document #: 38-05668 Rev. *B
Page 15 of 15

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